I have a problem in using generate statement in the following SystemVerilog code. The following code generates the connections in the inner loop(i), only for the cases j=0 and j=1; not for the cases j=2 and j=3 (ie. for the cases j>i). If I change the i to i=3, this will generate the connections for j=0, j=1 and j=2.
This should be a silly mistake; but I am not able to figure it out. Could anyone please help?
`define N_PORTS 2
`define N_CHANNELS 4
logic [`N_PORTS-1 : 0] input_to_channel [`N_CHANNELS-1 : 0];
logic [`N_PORTS-1 : 0] to_ch0,
to_ch1,
to_ch2,
to_ch3,
to_ch4,
to_ch5,
to_ch6,
to_ch7;
genvar i,j;
generate
for(j=0; j<`N_CHANNELS; j=j+1)
begin
case (j)
0:
for(i=0; i<`N_PORTS; i=i+1)
begin
assign input_to_channel[j][i] = to_ch0[i];
end
1:
for(i=0; i<`N_PORTS; i=i+1)
begin
assign input_to_channel[j][i] = to_ch1[i];
end
2:
for(i=0; i<`N_PORTS; i=i+1)
begin
assign input_to_channel[j][i] = to_ch2[i];
end
3:
for(i=0; i<`N_PORTS; i=i+1)
begin
assign input_to_channel[j][i] = to_ch3[i];
end
endcase
end
endgenerate
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var-window = struct_from_data(S); % values contains inputs
correspond(S, S, DOING_R, ENVIRONMENT,R); % state values

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It was generated by a neural network.